Gate Level Description Study Materials
Identify logic gate primitives provided in Verilog.
• Understand instantiation of gates, gate symbols, and truth tables for and/or and buf/not type gates.
• Understand how to construct a Verilog description from the logic diagram of the circuit.
• Describe rise, fall, and turn-off delays in the gate-level design.
• Explain min, max, and typical delays in the gate-level design.
Identify logic gate primitives provided in Verilog.
• Understand instantiation of gates, gate symbols, and truth tables for and/or and buf/not type gates.
• Understand how to construct a Verilog description from the logic diagram of the circuit.
• Describe rise, fall, and turn-off delays in the gate-level design.
• Explain min, max, and typical delays in the gate-level design.
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