Behavioral Description study materials

•• The significance of structured procedures always and initial in behavioral modeling.

•• Define blocking and nonblocking procedural assignments.

•• Understand delay-based timing control mechanism in behavioral modeling. Use regular delays, intra-assignment delays, and zero delays.

•• Describe event-based timing control mechanism in behavioral modeling. Use regular event control, named event control, and event OR control.

•• Use level-sensitive timing control mechanism in behavioral modeling.

•• Explain conditional statements using if and else.

•• Describe multiway branching, using case, casex, and casez statements.

•• Understand looping statements such as while, for, repeat, and forever.

•• Define sequential and parallel blocks.

•• Understand naming of blocks and disabling of named blocks.

•• Use behavioral modeling statements in practical examples.

Data flow description Study materials

Learning Objectives

• Describe the continuous assignment (assign) statement, restrictions on the assign statement, and the implicit continuous assignment statement.

• Assignment delay, implicit assignment delay, and net declaration delay for continuous assignment statements.

• Define expressions, operators, and operands.

• List operator types for all possible operations.

arithmetic, logical, relational, equality, bitwise, reduction, shift, concatenation, and conditional.

• Use dataflow constructs to model practical digital circuits in Verilog.

Gate Level Description Study Materials

Identify logic gate primitives provided in Verilog.
• Understand instantiation of gates, gate symbols, and truth tables for and/or and buf/not type gates.
• Understand how to construct a Verilog description from the logic diagram of the circuit.
• Describe rise, fall, and turn-off delays in the gate-level design.
• Explain min, max, and typical delays in the gate-level design.

Modules and ports Study Materials

Identify the components of a Verilog module definition, such as module names, port lists, parameters, variable declarations, dataflow statements, behavioral statements, instantiation of other modules, and tasks or functions.
• Understand how to define the port list for a module and declare it in Verilog.
• Describe the port connection rules in a module instantiation.
• Understand how to connect ports to external signals, by ordered list, and by name.
• Explain hierarchical name referencing of Verilog identifiers.

Verilog program for 8:3 Encoder with Priority

module priorityencoder(en,a,y);

input en;

input [7:0]a;

output [2:0]y;

reg [2:0]y;

always@ (en,a)

begin

if (en==1'b1)

y=3'bZZZ;

else if (a[7]==1) y=3'b111;

else if (a[6]==1) y=3'b110;

else if (a[5]==1) y=3'b101;

else if (a[4]==1) y=3'b100;

else if (a[3]==1) y=3'b011;

else if (a[2]==1) y=3'b010;

else if (a[1]==1) y=3'b001;

else if (a[0]==1) y=3'b000;

else

y=3'bZZZ;

end

endmodule

INPUTS									OUTPUTS
en	a(7)	a(6)	a(5)	a(4)	a(3)	a(2)	a(1)	a(0)	b(2)	b(1)	b(0)
0	0	0	0	0	0	0	0	1	0	0	0
0	0	0	0	0	0	0	1	-	0	0	1
0	0	0	0	0	0	1	-	-	0	1	0
0	0	0	0	0	1	-	-	-	0	1	1
0	0	0	0	1	-	-	-	-	1	0	0
0	0	0	1	-	-	-	-	-	1	0	1
0	0	1	-	-	-	-	-	-	1	1	0
0	1	-	-	-	-	-	-	-	1	1	1
0	0	0	0	0	0	0	0	0	Z	Z	Z
1	-	-	-	-	-	-	-	-	Z	Z	Z