Modules and ports Study Materials
Identify the components of a Verilog module definition, such as module names, port lists, parameters, variable declarations, dataflow statements, behavioral statements, instantiation of other modules, and tasks or functions.
• Understand how to define the port list for a module and declare it in Verilog.
• Describe the port connection rules in a module instantiation.
• Understand how to connect ports to external signals, by ordered list, and by name.
• Explain hierarchical name referencing of Verilog identifiers.
Identify the components of a Verilog module definition, such as module names, port lists, parameters, variable declarations, dataflow statements, behavioral statements, instantiation of other modules, and tasks or functions.
• Understand how to define the port list for a module and declare it in Verilog.
• Describe the port connection rules in a module instantiation.
• Understand how to connect ports to external signals, by ordered list, and by name.
• Explain hierarchical name referencing of Verilog identifiers.
No comments:
Post a Comment