Verilog program for 8:3 Encoder with Priority
module priorityencoder(en,a,y);
input en;
input [7:0]a;
output [2:0]y;
reg [2:0]y;
always@ (en,a)
begin
if (en==1'b1)
y=3'bZZZ;
else if (a[7]==1) y=3'b111;
else if (a[6]==1) y=3'b110;
else if (a[5]==1) y=3'b101;
else if (a[4]==1) y=3'b100;
else if (a[3]==1) y=3'b011;
else if (a[2]==1) y=3'b010;
else if (a[1]==1) y=3'b001;
else if (a[0]==1) y=3'b000;
else
y=3'bZZZ;
end
endmodule|
INPUTS
|
OUTPUTS
|
||||||||||
|
en
|
a(7)
|
a(6)
|
a(5)
|
a(4)
|
a(3)
|
a(2)
|
a(1)
|
a(0)
|
b(2)
|
b(1)
|
b(0)
|
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
-
|
0
|
0
|
1
|
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
-
|
-
|
0
|
1
|
0
|
|
0
|
0
|
0
|
0
|
0
|
1
|
-
|
-
|
-
|
0
|
1
|
1
|
|
0
|
0
|
0
|
0
|
1
|
-
|
-
|
-
|
-
|
1
|
0
|
0
|
|
0
|
0
|
0
|
1
|
-
|
-
|
-
|
-
|
-
|
1
|
0
|
1
|
|
0
|
0
|
1
|
-
|
-
|
-
|
-
|
-
|
-
|
1
|
1
|
0
|
|
0
|
1
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
1
|
1
|
1
|
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
Z
|
Z
|
Z
|
|
1
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
Z
|
Z
|
Z
|
