Verilog code for Decoder 2 to 4

module decoder2_4 (din, enable, d_out);

input [1:0] din;

input enable;

output [3:0] d_out;

reg [3:0] d_out;

always@(din,enable)

begin

      if (enable)

            d_out=4’b0000;

      else

            case (din)

            2'b00: d_out = 4'b0001;

            2'b01: d_out = 4'b0010;

            2'b10: d_out = 4'b0100;

            2'b11: d_out = 4'b1000;

            default: d_out =4'bxxxx;

            endcase

end

endmodule

enable	din(1)	din(0)	outputs
			d_out(3)	d_out(2)	d_out(1)	d_out(0)
1	X	X	0	0	0	0
0	0	0	0	0	0	1
0	0	1	0	0	1	0
0	1	0	0	1	0	0
0	1	1	1	0	0	0