module
encoder8_3(enable, din, d_out);
input
enable;
input
[7:0] din;
output
[2:0] d_out;
reg
[2:0] d_out;
always
@ (din, enable)
begin
if(enable==1 )
d_out=3’b000;
else
case (din)
8'b00000001: d_out = 3'b000;
8'b00000010: d_out = 3'b001;
8'b00000100: d_out = 3'b010;
8'b00001000: d_out = 3'b011;
8'b00010000: d_out = 3'b100;
8'b00100000: d_out = 3'b101;
8'b01000000: d_out = 3'b110;
8'b10000000: d_out = 3'b111;
default: d_out =3'bxxx;
endcase
end
endmodule
inputs
|
outputs
|
||||||||||
enable
|
din(0)
|
din(1)
|
din(2)
|
din(3)
|
din(4)
|
din(5)
|
din(6)
|
din(7)
|
d_out
(0) |
d_out
(1) |
d_out
(2) |
1
|
x
|
x
|
x
|
x
|
x
|
x
|
x
|
x
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
1
|
1
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
1
|
1
|
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