Data flow description Study materials

Learning Objectives

• Describe the continuous assignment (assign) statement, restrictions on the assign statement, and the implicit continuous assignment statement.

• Assignment delay, implicit assignment delay, and net declaration delay for continuous assignment statements.

• Define expressions, operators, and operands.

• List operator types for all possible operations.

arithmetic, logical, relational, equality, bitwise, reduction, shift, concatenation, and conditional.

• Use dataflow constructs to model practical digital circuits in Verilog.

Gate Level Description Study Materials

Identify logic gate primitives provided in Verilog.
• Understand instantiation of gates, gate symbols, and truth tables for and/or and buf/not type gates.
• Understand how to construct a Verilog description from the logic diagram of the circuit.
• Describe rise, fall, and turn-off delays in the gate-level design.
• Explain min, max, and typical delays in the gate-level design.

Modules and ports Study Materials

Identify the components of a Verilog module definition, such as module names, port lists, parameters, variable declarations, dataflow statements, behavioral statements, instantiation of other modules, and tasks or functions.
• Understand how to define the port list for a module and declare it in Verilog.
• Describe the port connection rules in a module instantiation.
• Understand how to connect ports to external signals, by ordered list, and by name.
• Explain hierarchical name referencing of Verilog identifiers.