VTU Syllabus

Verilog HDL Syllabus

Module-1
Overview of Digital Design with Verilog HDL
Evolution of CAD, emergence of HDLs, typical HDL-flow, why Verilog HDL?, trends in HDLs. (Text1)
Hierarchical Modeling Concepts
Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block. (Text1)
Module-2
Basic Concepts
Lexical conventions, data types, system tasks, compiler directives. (Text1)
Modules and Ports
Module definition, port declaration, connecting ports, hierarchical name referencing.
(Text1)
Module-3
Gate-Level Modeling
Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays. (Text1)
Dataflow Modeling
Continuous assignments, delay specification, expressions, operators, operands, operator types. (Text1)
Module-4
Behavioral Modeling
Structured procedures, initial and always, blocking and non-blocking statements, delay control, generate statement, event control, conditional statements, multiway branching, loops, sequential and parallel blocks. (Text1)
Module-5
Introduction to VHDL
Introduction: Why use VHDL?, Shortcomings, Using VHDL for Design Synthesis, Design tool flow, Font conventions. Entities and Architectures: Introduction, A simple design, Design entities, Identifiers, Data objects, Data types, and Attributes. (Text 2)
Text Books:
1. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson Education, Second Edition.
2. Kevin Skahill, “VHDL for Programmable Logic”, PHI/Pearson education, 2006.