Verilog Code for Logic Gates

module logic_gates(a, b, not_out, and_out, nand_out, or_out, nor_out, xor_out, xnor_out);

input a,b;
output not_out,and_out,nand_out,or_out,nor_out,xor_out,xnor_out;

assign not_out=~a;
assign and_out=a&b;
assign nand_out=~(a&b);
assign or_out=a|b;
assign nor_out=~(a|b);
assign xor_out=a^b;
assign xnor_out=~(a^b);

endmodule